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Sheet目录3873

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2010 Microchip Technology Inc.

DS21801F-page 33

MCP2515

4.5.3

FILHIT BITS

Filter

matches

received

messages

can

determined by the FILHIT bits in the associated

RXBnCTRL register. RXB0CTRL.FILHIT0 for buffer 0

and RXB1CTRL.FILHIT<2:0> for buffer 1.

The three FILHIT bits for receive buffer 1 (RXB1) are

coded as follows:

- 101 = Acceptance Filter 5 (RXF5)

- 100 = Acceptance Filter 4 (RXF4)

- 011 = Acceptance Filter 3 (RXF3)

- 010 = Acceptance Filter 2 (RXF2)

- 001 = Acceptance Filter 1 (RXF1)

- 000 = Acceptance Filter 0 (RXF0)

RXB0CTRL contains two copies of the BUKT bit and

the FILHIT<0> bit.

The coding of the BUKT bit enables these three bits to

be used similarly to the RXB1CTRL.FILHIT bits and to

distinguish a hit on filter RXF0 and RXF1 in either

RXB0 or after a roll over into RXB1.

- 111 = Acceptance Filter 1 (RXB1)

- 110 = Acceptance Filter 0 (RXB1)

- 001 = Acceptance Filter 1 (RXB0)

- 000 = Acceptance Filter 0 (RXB0)

If the BUKT bit is clear, there are six codes

corresponding to the six filters. If the BUKT bit is set,

there are six codes corresponding to the six filters, plus

two additional codes corresponding to RXF0 and RXF1

filters that roll over into RXB1.

4.5.4

MULTIPLE FILTER MATCHES

If more than one acceptance filter matches, the FILHIT

bits will encode the binary value of the lowest

numbered filter that matched. For example, if filter

RXF2 and filter RXF4 match, FILHIT will be loaded with

the value for RXF2. This essentially prioritizes the

acceptance filters with a lower-numbered filter having

higher priority. Messages are compared to filters in

ascending order of filter number. This also ensures that

the message will only be received into one buffer. This

implies that RXB0 has a higher priority than RXB1.

4.5.5

CONFIGURING THE MASKS AND

FILTERS

The mask and filter registers can only be modified

when the MCP2515 is in Configuration mode (see

Section 10.0 “Modes of Operation”).

FIGURE 4-5:

MESSAGE ACCEPTANCE MASK AND FILTER OPERATION

Note:

000

and 001 can only occur if the BUKT bit

in RXB0CTRL is set, allowing RXB0

messages to roll over into RXB1.

Note:

The mask and filter registers read all '0'

when in any mode except Configuration

mode.

Acceptance Filter Register

Acceptance Mask Register

RxRqst

Message Assembly Buffer

RXFn0

RXFn1

RXFnn

RXMn0

RXMn1

RXMnn

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